Pitcher&#39;s workout machine

ABSTRACT

The pitcher&#39;s workout machine has a frame assembly which includes three rectangular light panel frames connected to define a box shaped target zone. The first and second frames mount infrared transmitters and receivers in a pattern defining a rectangular strike zone, with a ball zone above, below, and on opposite sides of the strike zone. Lenses are used to collimate the infrared beams. When a ball passes through the frame assembly, the first frame triggers a pulse generator and the third frame stops the pulse generator. Shift registers count the pulses, and the speed is determined by the predetermined distance between the first and third frames. Shift registers count balls and strikes, and calculate the number of balls, strikes, walks, outs, and innings, which are displayed on a display panel.

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This is a continuation-in-part of my prior application Ser. No. 09/523,580, filed Mar 10, 2000, which is a continuation-in-part of application Ser. No. 08/982,063, filed Dec. 1, 1997, now abandoned.

BACKGROUND OF THE INVENTION 1. Field of the Invention

[0002] The present invention relates to a pitcher's workout machine which is to be used by baseball pitchers for the purpose of improving and evaluating their skills using a standard hard ball or soft ball.

[0003] 2. Description of the Related Art

[0004] Baseball and softball players try to improve their pitching ability by practicing to pitch. In normal pitching practice, baseball pitchers practice their skill by throwing balls at baseball catchers. This takes two people to practice. It does not record the speed, the balls, the strikes, or the outs. Baseball pitchers also improve and practice their skill by throwing balls at apparatus designed for intercepting the balls thrown. Such apparatus normally have a strike zone located in the center. These apparatus help a pitcher by showing him/her where the balls are hitting on the apparatus. These apparatus are usually made of canvas material. The strike zone has a dark color with respect to the rest of the canvas material, which is usually white. The strike zone usually has a pouch for holding balls that pass through that zone. These systems do not record the ball speed of thrown balls, the number of balls thrown, the number of strikes thrown, or the number of outs thrown. A representative purely mechanical target system with no electronic mechanisms for determining the location or speed of the ball is shown in U.S. Pat. No. 4,978,121, issued December, 1990 to R. Larkey (portable pitching mound and target).

[0005] Several devices have been developed with electronic systems for detecting the position and/or speed of a thrown baseball. Some of these devices use mechanical switches or flexible grids to determine location, such as: U.S. Pat. No. 2,251,305, issued Aug. 5, 1941 to J. P. Tarbox (arcade device where ball hits a strike receptacle and travels in a channel. tripping a switch); U.S. Pat. No. 5,046,729, issued September, 1991 to W. E. Yancey (ball strikes panels resiliently mounted on backboard, closing momentary switches); U.S. Pat. No. 5,064,194, issued November, 1991 to Bixler et al. (ball strikes hinged panel, the hinges opening and closing switches); U.S. Pat. No. 5,419,565, issued May, 1995 to Gordon et al. (strikes wire grid connected to piezoelectric elements, or strikes grid of magnetic strips); U.S. Pat. No. 5,553,860, issued September, 1996 to R. Zelikovitch (target is piezoelectric film which modulates an RF carrier for remote operation); U.S. Pat. No. 5,658,211, issued August, 1997 to C. G. Glover (arcade game simulating a squeeze play where ball goes through a hole and hits access plate, actuating a switch); U.S. Pat. No. 5,820,496, issued October, 1998 to R. W. Bergeron (backstop with cable grid); and U.S. Pat. No. 5,566,934, issued October, 1996 to Black et al. (first switch activated when pitcher's foot leaves rubber, second switch activated by hinged ball or strike target).

[0006] An early optical device is described by J. Oram in U.S. Pat. No. 2,113,899, issued April, 1938. The Oram device has one lamp directed vertically downward through a slit the width of home plate, where the beam is reflected by a mirror through a condenser lens to a photocell, and a second lamp directed horizontally to a plurality of mirrors which reflect the beam through a second condenser lens to a second photocell, an indicator showing a strike when both beams are broken.

[0007] U.S. Pat. No. 4,563,005, issued January, 1986 to Hand et al., shows a baseball pitching performance apparatus with two parallel target zones, each target zone having two parallel vertical posts with an array of sequentially triggered infrared emitters and a pair of receivers at the top and bottom of each post, respectively. The position is calculated by a computer using the law of sines, and the speed using the transit time between the two zones.

[0008] U.S. Pat. No. 4,949,972, issued August, 1990 to Goodwin et al., teaches a device for target shooting scoring which has an X-Y grid of infrared LED's and a computer to determine the location a bullet strikes a paper target. The device specifically does not use lenses to focus the LED's on receivers, and does not compute projectile speed.

[0009] U.S. Pat. No. 5,230,505, issued July, 1993 to Paquet et al., describes an apparatus for evaluating baseball pitching performance having a first plane of horizontally oriented IR emitter-receiver pairs, and a second plane of vertically oriented IR-emitter-receiver pairs spaced apart from the first plane, preferably by twelve inches. A microcontroller receives inputs in groups of eight and computes the position from the grid. Speeding is determined by recording the time that the ball breaks the two planes and using the formula Speed=1/(t₂−t₁)×constant. Paquet does not teach the use of lenses to focus the IR beams.

[0010] U.S. Pat. No. 5,577,733, issued November, 1996 to D. L. Downing, shows a device for evaluating target shooting which does not use a fixed target zone, but a target projected by a computer. FIGS. 3-4 and col. 13, lines 44-65 show an X-Y grid of beams collimated by lenses built into the emitters' mount, and uses two spaced apart light panels to compute speed by computer recorded times or by times calculated by electronics at the light posts and fed to the computer, the nature of the electronics at the posts not being shown. Downing does not teach mounting focusing lenses on a separate post between emitter and receiver, and does not teach a dead zone corresponding to a fixed target width.

[0011] U.S. Pat. No. 5,602,638, issued February, 1997 to J. L. Boulware, discloses a device for determining a moving ball's position and speed having grids of IR transmitters and receivers in which alternating IR transmitters are 180° out of phase. A microprocessor is used to calculate the ball's speed.

[0012] U.S. Pat. No. 5,509,649, issued April, 1996 to D. R. Buhrkuhl, teaches a device having a frame adjusted to the height of a strike zone, with only a single row of IR transmitter-receiver pairs. Alternating transmitters are 180° out of phase. On the assumption that a ball traveling at 100 m.p.h. requires 0.0017045 seconds to traverse the IR beam, the device uses a 555 timer to set the IR transmitters to pulse at 586.67 Hz. The device counts the pulses blocked when a balls traverses the beams, and deducts 1 m.p.h. from 100 for each pulse blocked. The device does not use lenses to focus the IR beams, and does count balls and strikes, outs or innings. The assumption that 1 m.p.h. is equivalent to one pulse is questionable, particularly as the speed of the ball decreases below 100 m.p.h.

[0013] Less relevant are patents used for golf training, such as U.S. Pat. No. 5,568,250, issued October, 1996 to Nishiyama et al., and U.S. Pat. No. 5,626,526, issued May, 1997 to Pao et al., which uses laser beams to detect the flight of the golf ball, but use trajectory mathematics and simultaneous equations to compute speed.

[0014] None of the above patents show a baseball pitching machine having a frame with a separate lens mounting post disposed between an array of infrared transmitters and receivers in order to collimate a beam to prevent interference between adjacent beams and to lengthen the range of the beams. None of the above patents show a baseball pitching machine with a dead zone in an array of IR beams extending for the width of the plate in order to reduce the cost of the apparatus. None of the above patents show a baseball pitching machine using an oscillator with a three way gate and shift registers to count the number of pulses occurring in the transit time between two parallel planes of IR beams. Finally, none of the above patents show a baseball pitching machine with circuitry for recording the number of balls and strikes, outs, walks, and innings, as well as the speed of each ball pitched.

[0015] None of the above inventions and patents, taken either singularly or in combination, is seen to describe the instant invention as claimed.

SUMMARY OF THE INVENTION

[0016] The pitcher's workout machine has a frame assembly which includes three rectangular light panel frames connected to define a box shaped target zone. The first and second frames mount infrared transmitters and receivers in a pattern defining a rectangular strike zone, with a ball zone above, below, and on opposite sides of the strike zone. Lenses are used to collimate the infrared beams. When a ball passes through the frame assembly, the first frame triggers a pulse generator and the third frame stops the pulse generator. Shift registers count the pulses, and the speed is determined by the predetermined distance between the first and third frames. Shift registers count balls and strikes, and calculate the number of balls, strikes, walks, outs, and innings, which are displayed on a display panel.

[0017] In order to decrease the number of parts and cost of the machine, the first frame defines an array of horizontally aligned infrared beams for the entire height of the frame, including a region above and below the strike zone, while the second frame defines an array of vertically aligned infrared beams which are spaced apart by the width of the strike zone, so that a ball is registered when both a horizontal and a vertical beam are interrupted by passage of the ball, while a strike is registered when the ball interrupts only a horizontal beam, unless the ball is above or below the strike zone, in which case a ball is registered.

[0018] Accordingly, it is a principal object of the invention to provide a pitcher's workout machine which uses arrays of infrared beams in which the beams are focused by lenses between the transmitters and receivers in order to reduce interference between adjacent transmitter-receiver pairs, and to extend the range of the beams.

[0019] It is another object of the invention to provide a pitcher's workout machine having ball and strike zones defined by orthogonal infrared beams in which the strike zone is defined by a dead zone in the vertical array of infrared beams, together with a region above and below the strike zone.

[0020] It is a further object of the invention to provide a pitcher's workout machine in which the speed of a pitched ball is determined by the predetermined, fixed distance between two parallel planes of infrared beams, and by using shift registers used to count pulses from a pulse generator having start and stop times triggered by passage of the ball through the parallel planes of beams, thereby avoiding the expense of a computer, microcontroller, microprocessor, or radar gun for determination of the velocity of a pitched ball.

[0021] Still another object of the invention is to provide a pitcher's workout machine that displays an out when three strikes are thrown, or a ball if four balls are thrown before three strikes, and which displays the number of outs and innings based on pitch location, all without the necessity of a computer, microprocessor, or microcontroller to perform calculations.

[0022] It is an object of the invention to provide improved elements and arrangements thereof for the purposes described which is inexpensive, dependable and fully effective in accomplishing its intended purposes.

[0023] These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a front perspective view of a pitcher's workout machine according to the present invention showing the skeleton of the frame assembly.

[0025]FIG. 2 is a front perspective view of a pitcher's workout machine according to the present invention, the control panel assembly being omitted, showing the relative placement of IR transmitters, receivers and focusing lenses.

[0026]FIG. 3 is a front perspective view of a frame assembly according to the present invention.

[0027]FIG. 4 is a front view of the first frame of the frame assembly according to the present invention, the third frame being identical.

[0028]FIG. 5 is a front view of the second frame of the frame assembly according to the present invention.

[0029]FIG. 6 is a fragmented front cutaway view of the first frame of the frame assembly according to the present invention.

[0030]FIG. 7 is a front view of the control panel assembly according to the present invention.

[0031]FIG. 8 is a front view of the display panel assembly according to the present invention.

[0032]FIG. 9 is a block diagram of the pitcher's workout machine according to the present invention.

[0033]FIG. 10 is a circuit diagram of the transmitter board according to the present invention.

[0034]FIG. 11 is a circuit diagram of the receiver board according to the present invention.

[0035]FIG. 12 is a schematic representation of the ball detection zones and strike detection zones of the pitcher's workout machine according to the present invention.

[0036]FIG. 13 is a block diagram showing the circuitry used to display strikes, outs and innings on the pitcher's workout machine according to the present invention.

[0037]FIG. 14 is a block diagram showing the circuitry used to count strikes in the pitcher's workout machine according to the present invention.

[0038]FIG. 15 is a block diagram showing the circuitry used to display balls and walks on the pitcher's workout machine according to the present invention.

[0039]FIG. 16 is a block diagram showing the circuitry used to display strikes, outs and innings on the pitcher's workout machine according to the present invention.

[0040]FIG. 17 is a partial schematic diagram showing a speed counter circuit according to the present invention.

[0041]FIG. 18 is a schematic diagram showing a driver circuit for illuminating a maximum speed exceeded display lamp according to the present invention.

[0042]FIG. 19 is a schematic diagram showing the segments of the display digits of the pitcher's workout machine according to the present invention.

[0043]FIG. 20 is a block diagram showing the display driver procedure for the strikes display in a pitcher's workout machine according to the present invention.

[0044] Similar reference characters denote corresponding features consistently throughout the attached drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] The present invention is a pitcher's workout machine. The invention disclosed herein is, of course, susceptible of embodiment in many different forms. Shown in the drawings and described hereinbelow in detail are preferred embodiments of the invention. It is to be understood, however, that the present disclosure is an exemplification of the principles of the invention and does not limit the invention to the illustrated embodiments. The disclosure of parent application Ser. No. 08/982,063 filed on Dec. 12, 1997, now abandoned, and parent application Ser. No. 09/523,580, filed Mar. 10, 2000, are hereby incorporated by reference.

[0046] Referring now to FIGS. 1 and 2, the pitcher's workout machine 10 comprises four interconnected assemblies. The four assemblies include a rack assembly 12, a frame assembly 14, a control panel assembly 16, and a display panel assembly 18. The four assemblies are electrically interconnected by wire cabling. The rack assembly 12 is mounted atop the frame assembly 14, and supports five circuit boards, including a power supply board 20, a transmitter board 22, a receiver board 24, a main logic board 26, and a display driver board 28. The power supply board 20 contains a dual power supply, including a +5 volt D.C. at 2 amperes and a +12 volt D.C. at 3 amperes, regulated. The twelve volt power supply is used to power the display panel assembly 18 and display drivers 28, while the five volt regulated supply is used to power the circuits for the remaining circuit boards. Five volt and twelve volts regulated power supplies are well known to those skilled in the electronics art, and will not be described further. Structurally, the circuit boards may be breadboards, perforated board, or printed circuit boards, as known in the art. The rack assembly 12 includes a backboard 30 rising from a top plate 32, the display assembly 18 being mounted on the backboard 30. As shown in FIG. 1, the control panel assembly 16 is mounted to the front of the rack assembly 12.

[0047] The frame assembly 14 is shown in more detail in FIGS. 3 through 6. The frame assembly 14 includes a first light panel frame 34, a second light panel frame 36, and a third light panel frame 38. The first 34 and third 38 light panel frames have identical structures, illustrated in FIG. 4. Each of the frames 34 and 38 are one hundred fifty centimeters square and are made from 5×5 cm posts. For clarity, the left vertical post is referred to as the transmitter post 40 and the right vertical post is referred to as the receiver post 42. A fifth 5×5 cm post, referred to as the lens post 44, is mounted vertically within the frame 34 about ten centimeters from the transmitter post 40, although the distance may vary depending upon the focal point of the lenses used.

[0048] The second light panel frame 36 has a similar construction, except for the orientation of the transmitter 40, receiver 42, and lens 44 posts. As shown in FIG. 5, the second light panel frame is also one hundred fifty centimeters square and made from 5×5 cm posts. However, in the second light panel frame 36 the transmitter post 40 is the top horizontal rail and the receiver post 42 is the bottom horizontal rail. The lens post 44 is aligned horizontally between the transmitter post 40 and receiver post 42, and spaced apart from the transmitter post 40 by about ten centimeters.

[0049] As shown in FIG. 3, the first light panel frame 34 and the second light panel frame 36 are mounted back to back in flush or abutting contact. The third light panel frame 38 is connected to the first 34 and second 36 frames by four transverse posts 46, defining a box shaped target zone 48 extending between the first frame 34 and the third frame 38.

[0050] As shown in FIG. 6, each transmitter post 40 has a linear array of infrared LED transmitters 50 mounted therein. Each transmitter mounting hole has a mounting well five millimeters in diameter and five millimeters deep towards the outside of the frame. The hole then expands in diameter to between about 3.3 to 3.85 centimeters towards the inside of the frame, and is painted white on the interior. Each lens post 44 has a linear array of lenses 52 aligned with the array of transmitters 50. Each lens 52 is mounted in a lens mounting hole 54 having a uniform diameter which may be in the range of about 3.3 to 3.85 centimeters extending through the lens post 44 and painted white on the interior. Each receiver post 42 has an array of phototransistor receivers 56 mounted therein in registry with the array of lenses 52. Each receiver 56 has a mounting well five millimeters in diameter and five millimeters deep towards the outside of the frame. The hole then expands in diameter to between about 3.3 to 3.85 centimeters towards the inside of the frame, and is painted white on the interior.

[0051] The lenses 52 are positive or convex lenses which focus the light emitted by the infrared LED transmitters 50 into collimated beams R₁, R₂ and R₃ having a diameter d of about three centimeters and which are spaced apart between two and three centimeters. Any light rays transmitted at an angle between the transmitter post 40 and the lens post 44 are blocked by the lens post 44 so that there is no interference between light beams emitted by adjacent transmitters 50. The advantage of interposing convex lenses 52 between the transmitters 50 and receivers 56 is that the beams are collimated into parallel rays R₁, R₂ and R₃ so that there is no interference between adjacent beams, thereby improving the accuracy of the machine's ability to discriminate a ball from a strike. An additional advantage is that the lenses 52 permit the beams R₁, R₂ and R₃ to be concentrated for a greater distance, thereby permitting the machine 10 to have a larger target area than devices which do not utilize focusing lenses.

[0052] As shown in FIGS. 3 and 4, the first light panel frame 34 and the third light panel frame 38 have a continuous array of uniformly spaced transmitters 50 extending from the bottom of the transmitter post 40 to about ten centimeters from the top of the post. Preferably, each transmitter post 40, lens post 44, and receiver post 42 mounts twenty-five transmitters 50, lenses 52, and receivers 56, respectively. On the other hand, as shown in FIGS. 3 and 5, the second light panel frame 36 has an array of about eighteen transmitters 50, lenses 52, and receivers 56 extending from the right side of the frame 34 to about ten centimeters from the left side of the frame 34, which is interrupted by a dead zone of about forty centimeters, corresponding to the width of the strike zone, so that the beams emitted by the second frame 36 are symmetrically disposed on opposite sides of the dead zone. The resulting ball detection area is depicted schematically in FIG. 12.

[0053] In FIG. 12 the horizontal lines represent the beams emitted by the first light panel frame 34. The vertical tick lines represent the beams emitted by the second light panel frame 36. (The number of lines shown in FIG. 12 is not to scale, the drawing being schematic). The first light panel frame 34 emits twenty-five horizontal beams, of which a central section of seven beams are strike lines 60, the remaining beams being symmetrically disposed above and below the strike lines 60 and defining ball lines 62. The second light panel frame 36 emits eighteen vertical beams, with nine beams each symmetrically disposed on opposite sides of a dead zone 64. Each vertical beam is therefore a ball line. If a ball traversing the target zone 48 interrupts even one beam representing a ball line, then the machine 10 registers the pitch as a “ball”. If a ball traversing the target zone 48 interrupts only beams representing strike lines, then the machine 10 registers the pitch as a “strike”.

[0054] For example, in FIG. 12, ball A interrupts two strikes lines, but no ball lines, so the machine 10 registers the pitch as a strike. Ball B is low and interrupts one ball line emitted by the first frame 34, and is registered as a ball. Balls C and D interrupt one strike line and one ball line emitted by the first frame 34 and at least one ball line emitted by the second frame, and are therefore registered as a ball.

[0055]FIG. 7 depicts the external appearance of the control panel assembly 16. The control panel assembly 16 is made from a rectangular board 66, which may be a breadboard, perforated board, printed circuit board, or the like. The board 66 has indicia 68 printed thereon which includes instructions for operation of the machine 10 and labels for four switches mounted on the board. The switches include a miniature two-position toggle switch used as a power switch 70 to turn electrical power on and off, and three miniature, normally closed momentary switches. One of the momentary switches is a strike switch 72 for setting the strike circuits, out circuits, and innings circuits to begin operation and for resetting “STRIKES”, “OUTS”, and “INNINGS” to zero on the display. A second momentary switch is a ball switch 74 for setting the balls and walks circuits to begin operation and for resetting “BALLS” and “WALKS” to zero on the display. A third momentary switch is a speed switch 76 for setting the speed circuits to begin operation and for resetting “SPEED” to zero on the display.

[0056]FIG. 8 depicts the external appearance of the display panel assembly 18. The display panel assembly 18 is made from a rectangular board 78, which may be a breadboard, perforated board, printed circuit board, or other suitable panel mounting assembly. The display panel assembly 18 has a single miniature lamp 80 rated at 2.4 volts and 360 ma mounted in an appropriate socket and labelled with indicia 82 indicating that the speed of the pitch exceeds the maximum that the machine 10 can calculate. The display panel assembly 18 has a number of other displays which each comprise a pattern of similar miniature lamps defining one or more figure “8”'s, together with indicia identifying the information registered by the machine 10. Each figure “8” includes two parallel vertical lines having six miniature lamps each, and three parallel lines having two miniature lamps each. Appropriate driver circuitry is used to turn segments of the figure “8” on and off to display any digit between zero and nine. The information displayed includes INNING'S 84, OUT'S 86, SPEED 88, WALK'S 90, BALLS 92 and STRIKES 94.

[0057]FIG. 9 shows a simplified block diagram of the pitcher's workout machine. Each of the infrared LED transmitters 50 mounted on the first frame transmitter post 40 a, second frame transmitter post 40 b, and third frame transmitter post 40 c, respectively, are connected to identical transmitter circuits on the transmitter board 22 by appropriate wiring. For example, if there are twenty-five transmitters on first post 40 a, eighteen transmitters on second post 40 b, and twenty-five transmitters on third post 40 c, then there are sixty-eight identical transmitter circuits on transmitter board 22. Similarly, each of the phototransistor receivers 56 mounted on the first frame receiver post 42 a, the second frame receiver post 42 b, and the third frame receiver post 42 c are connected to identical receiver circuits on the receiver board 24. The circuits on receiver board 24 are connected to various circuits on the main logic board 26 which process the received signals and output corresponding signals to display driver board 28 which supplies the necessary voltage and current to change the displays on the display panel assembly 18 in response to the signals from the main logic board 26.

[0058]FIG. 10 illustrates a transmitter circuit 100 according to the present invention. U1 is a 555 timer integrated circuit configured to operate in the astable mode. The values of resistors R1 and R2 and capacitor C1 are selected so that the output of U1 at pin 3 produces a high-level logic pulse of about 1.7 milliseconds duration followed by a low level pulse of four hundred microseconds duration. This oscillating signal is coupled by capacitor C3 to the base of darlington pair transistors Q1 and Q2, which amplify the signal. Infrared LED 50 emits a signal having the oscillating signal as a pulsed infrared light beam to a corresponding receiver 52. There is a separate, identical transmitter circuit 100 on the transmitter board 22 for each transmitter 50 mounted on the frame assembly 14. Typical component values for the transmitter circuit 100 are as follows: TABLE 1 U1 555 timer R1 100 kΩ R2 1.1 kΩ R3 4.99 kΩ R4 1.5 Ω R5 110 kΩ R6 15 kΩ C1 0.022 μF C2 0.01 μF C3 47 μF Q1, Q2 2N2907 D1 F5D3 V_(CC) +5 volts

[0059]FIG. 11 illustrates a receiver circuit 102 according to the present invention. The receiver circuit is essentially a “missing pulse detector” circuit. Q3 is a phototransistor receiver 56 which receives the oscillating infrared signal transmitted by diode Dl, except when the beam is interrupted by passage of a ball through the beam. The oscillating signal is coupled by capacitor C5 to pin 2 (the trigger pin) of 555 timer U2, which is configured to operate in monostable mode. The output 104 at pin 3 of U2 is normally kept at a logic high voltage by C8-R9. C6-R8 is an RC charging circuit. When the voltage across C6 reaches ⅔ V_(cc), the output 104 at pin 3 switches to a low logic level. However, the C6-R8 RC time constant is selected so that the oscillating signal coupled through C5 applies a low logic level trigger pulse of 400 μs duration to pin 2 of U2 every 1.7 ms to reset U2, and to also forward bias transistor Q4, thereby discharging C6 to ground through Q4 before capacitor C6 is charged to ⅔ V_(cc), and thereby maintaining the output 104 at pin 3 of U2 at a logic high level. When a ball interrupts the beam between D1 and Q3 (between transmitter 50 and receiver 56), the trigger pulse is blocked from reaching pin 2 of U2, and C6 charges to ⅔ V_(cc), switching the output 104 of U2 at pin 3 to a low logic level. Capacitor C6 then discharges to ground through pin 7 of U2 and the output 104 of U2 resets to a high logic level. There is a separate, identical receiver circuit 102 on the receiver board 24 for each receiver 56 mounted on the frame assembly 14. Typical component values for the receiver circuit 102 are as follows: TABLE 2 Q3 L14P2 phototransistor Q4 2N2907 PNP R7 110 kΩ R8 50.3 kΩ R9 3.3 kΩ R10  1 MΩ R11  3.3 Ω C4 100 μF C5 47 μF C6 0.047 μF C7 0.01 μF C8 100 μF U2 555 timer IC V_(CC) +5 volts

[0060] Referring now to FIG. 13, the signals produced by the seven receiver circuits 102 connected to the phototransistor receivers 56 on first light panel frame 34 corresponding to the strike lines 60 are processed as follows. The multiple strike line input signals 110 from the receiver circuits are processed by a gate circuit 112 on the main logic board 26 to produce a single strike signal 114. Normally, the output signal from the receiver circuits 102 is a logic high. When a ball interrupts one of the strike lines 60, the output from the receiver circuit for that strike line goes from a logic high to a logic low. The gate circuit 112 is configured so that when all of the multiple strike line input signals 110 are a logic high, the single strike signal 114 is also a logic high, but when at least one strike line input signal 110 is a logic low, then the single strike signal 114 is a logic low.

[0061] Numerous circuit configurations are known in the art to accomplish the requirements of the gate circuit 112. In a preferred embodiment (not shown), multiple receiver signals are input to multiple input NOR gate integrated circuits, e.g., the 74f27 three-input NOR gate. The outputs from the NOR gates are tied together to control the bias voltage of a single small signal transistor, such as a 2N2222 NPN transistor. The single strike signal may be taken from the collector of the transistor.

[0062] A bias signal is derived from the single strike signal 114 and is coupled to the speed circuit 116 to trigger an oscillator as described below. The single strike signal 114 also triggers a timer 118, provided that the timer 118 does not receive an inhibit pulse from the circuitry for counting balls 119, i.e. if the pitch interrupts both a ball line 62 and a strike line 60, the pitch is counted as a ball, otherwise timer 118 is triggered to output a pulse which is counted by the strike counter circuitry. Timer 118 is a 555 integrated circuit timer configured to operate in monostable mode.

[0063] The pulse generated by the timer 118 is counted by a strike counter circuit 120. A block diagram of a representative strike counter circuit 120 is shown in FIG. 14. The strike counter circuit 120 includes a dual flip-flop 122 (e.g., a 74f74 dual D-type flip-flop), a shift register 124 (e.g., a 74f164 shift register, with three registers being used), a ten second timer 126, and a ten microsecond timer 128. When the machine 10 is first turned on, the user momentarily depresses strike switch 72 on the control panel assembly 16, which turns the flip-flop 122 output to a high logic level. This high logic output is used by a display driver wired to output a “0” on the strikes display 94. It also performs a master rest of shift register 124 and applies a high logic level to the input of the first register 124 a of shift register 124.

[0064] When a strike pulse is generated by timer 118, the high logic level is shifted to the output of first register 124 a and applied to the input of second register 124 b. This high logic level output is applied to a display driver wired to output a “1” on the strikes display 94. It also causes a reset signal 130 to be applied to the flip-flop 122, removing the high logic level applied to the “0” display driver and resetting the input to the first register 124 a. When a second strike pulse is received from timer 118, the high logic level is shifted from the input to the output of second register 124 b and applied to the input of third register 124 c. The high logic level at the output of second register 124 b is also applied to a display driver wired to output a “2” on the strikes display 94. When a third strike pulse is generated by timer 118, the high logic level is shifted from the input of third register 124 c to the output of the third register 124 c. This action causes three things to occur. First, the high logic level is applied to a display driver wired to output a “3” on the strikes display 94. Second, the high logic level is passed through an inverter to apply a trigger pulse to a 556 integrated circuit dual timer 126 which is configured to operate in monostable mode, and applies a reset pulse 132 after a ten second delay which has the same effect as closing the strike switch 72, i.e., it resets the strike display 94 to “0” and is applied to the master reset pin to clear the shift register 124. Third, the high logic level at the output of the third register 124 c applies a trigger pulse through an inverter to a 555 integrated circuit timer 128 configured to operate in a monostable mode which generates a ten microsecond pulse which is applied to an outs counter circuit 134. The effect is that the display assembly 118 displays the third strike for ten seconds, resets the strike display to “0”, and increments the outs display 86.

[0065] The ten microsecond pulse generated by timer 128 is applied as input to an outs counter circuit 134, which has the same configuration as strike counter circuit 120. The block diagram in FIG. 14 and the related discussion of circuit operation is therefore identical for the outs counter circuit, with three exceptions: (1) the ten microsecond pulse from timer 128 provides the input to first register 124 a; (2) the display drivers are wired to outs display 86 instead of strikes display 94; and (3) after three outs have been counted, the ten microsecond pulse produced by timer 128 is applied as input to the innings counter circuit 136.

[0066] Likewise, the innings counter circuit 136 has the same configuration as the strike counter circuit 120 shown in FIG. 14, with four exceptions: (1) the output pulse from outs counter circuit 134 provides the input to first register 124 a; (2) the display drivers are wired to innings display 84 instead of strikes display 94; (3) seven registers of the shift register 124 are used instead of three, in order to display up to seven innings; and (4) the ten microsecond timer 128 is eliminated, since there is no carry over pulse from the innings counter circuit 136.

[0067] Referring to FIG. 15, the signals produced by the eighteen receiver circuits 102 connected to the phototransistor receivers 56 on first light panel frame 34 corresponding to the ball lines 62 and all eighteen receiver circuits 102 connected to the phototransistor receivers 56 on second light panel frame 36 are processed as follows. The multiple ball line input signals 140 from the receiver circuits are processed by a gate circuit 142 on the main logic board 26 to produce a single ball signal 144. Normally, the output signal from the receiver circuits 102 is a logic high. When a ball interrupts one of the ball lines 62 of the first frame 34 or the second frame 36, the output from the receiver circuit for that ball line goes from a logic high to a logic low. The gate circuit 142 is configured so that when all of the multiple ball line input signals 140 are a logic high, the single ball signal 144 is also a logic high, but when at least one ball line input signal 140 is a logic low, then the single ball signal 144 is a logic low. The gate circuit 142 used to achieve this result is constructed in the same manner as gate circuit 112, and therefore will not be described further.

[0068] A bias signal 146 is derived from the single ball signal 144 and is coupled to the speed circuit to trigger an oscillator as described below. The single ball signal 144 also triggers a timer 148. Timer 148 is a 555 integrated circuit timer configured to operate in monostable mode. The pulse generated by the timer 148 provides an inhibit pulse 119 which is applied through an inverter to pin 4 (the reset pin) of timer 118 to prevent the pitch being counted as a strike if it simultaneously interrupts one of the strike lines 60. The pulse generated by the timer 148 is also counted by ball counter circuit 150. Ball counter circuit 150 has the same configuration as the strike counter circuit 120 described in FIG. 14, with the following differences: (1) ball switch 74 is substituted for strike switch 72, the user resetting the ball display 92 and the walk display 90 to “0” and resetting shift register 124 by depressing ball switch 74 when the machine is started; (2) the pulse output by timer 148 is applied as input to the first register 124 a; (3) four registers are used to count up to four balls; (4) the output from successive registers is used to drive display drivers wired to the balls display 92 instead of the strike display 92; (5) the ten microsecond pulse generated by timer 128 is applied as input to a walk counter circuit 152; and (6) the ten microsecond pulse generated by timer 128 is also applied to the strike counter circuit 120 between switch 72 and pin 1 of the flip-flop 122 in order to reset the strikes display 94 and the strikes shift register 124 to “0” strikes.

[0069] Similarly, the walk counter circuit 152 has the same configuration as the strike counter circuit 120 shown in FIG. 14 with the following exceptions: (1) ball switch 74 is substituted for strike switch 72; (2) the output pulse from ball counter circuit 150 provides the input to first register 124 a; (3) the display drivers are wired to walks display 90 instead of strikes display 94; (4) eight registers of the shift register 124 are used instead of three, in order to display up to eight walks; and (5) the ten microsecond timer 128 is eliminated, since there is no carry over pulse from the walk counter circuit 150.

[0070] The pitcher's workout machine calculates and displays the speed of the ball, provided that the speed is between fifty and one hundred miles per hour. In brief, when the ball interrupts either a ball line or a strike line in the first light panel frame 34, an oscillator is triggered, and when the ball interrupts the third light panel frame, a pulse is generated which stops the oscillator. Since the distance between the first frame and the third frame is fixed, the time required to traverse the distance at a given speed can be computed, and since the frequency of oscillation (and therefore the period) is fixed, the number of pulses can be counted by shift registers and the speed displayed according to a predetermined table which relates the speed to the number of pulses.

[0071]FIG. 16 shows a block diagram of a speed circuit 116 according to the present invention. The signals produced by the twenty-five receiver circuits 102 connected to the phototransistor receivers 56 on third light panel frame 38 are processed as follows. The multiple speed line input signals 160 from the receiver circuits are processed by a gate circuit 162 on the main logic board 26 to produce a single speed signal 164. Normally, the output signal from the receiver circuits 102 is a logic high. When a ball interrupts one of the speed lines of the third frame 38, the output from the receiver circuit for that speed line goes from a logic high to a logic low. The gate circuit 162 is configured so that when all of the multiple speed line input signals 160 are a logic high, the single speed signal 164 is also a logic high, but when at least one speed line input signal 160 is a logic low, then the single speed signal 164 is a logic low. The gate circuit 162 used to achieve this result is constructed in the same manner as gate circuit 112, and therefore will not be described further.

[0072] The speed circuit has a transistor switch 166, e.g., a bipolar NPN transistor. Normally the transistor is reverse biased by the output of a tri-state buffer 168, e.g., a 74f125, since the normally high logic level single speed signal 164 applies a high logic level to the buffer's enable pin, keeping the output of buffer 168 at a logic low level. When a ball traverses the target zone, the transistor switch receives two switching signals: the first is a bias voltage 116 or 146 received either from the strike circuit or the ball circuit, derived either from the single strike signal 114 or the single ball signal 144 as described above; the second is from the single speed signal 164.

[0073] When a bias voltage 116 or 146 is received from the strike circuit or the ball circuit, transistor switch 166 is turned on and applies a trigger voltage to first timer (a 555 integrated circuit timer) 170, which is configured in monostable mode and outputs a 10 μs pulse. This 10 μs pulse is inverted by inverter 172 (a two input NAND gate with the inputs tied together), and the inverted pulse is output to the speed driver board as an OUT MAX 2 signal 174, and is also applied as a trigger pulse to second timer 176, which is a 555 timer configured in monostable mode to generate an 8.225 millisecond (ms) pulse. This 8.225 ms pulse is output to the speed driver board as an OUT MAX 1 signal 178, is applied to the input of a D-type dual flip-flop 180, and applied to the enable pin of a second tri-state buffer 182. The flip-flop 180 has two outputs, the first being an OUT SPEED 2 184, the second being applied to the reset pin of a third timer 186, which is a 555 timer configured in astable mode to oscillate at 14650 Hz. The output of tri-state buffer 182 is normally low, but passes the pulses generated by third timer 166 when the 8.225 ms pulse goes to a low logic level as OUT SPEED 1 188. The purpose of the 8.225 ms delay is to prevent the first one hundred and twenty pulses output by third timer 186 from being counted by the speed counter circuit 190, for the reasons described below. Speed switch 76 is connected to the reset pin of flip-flop 180 so that when the user presses the switch at start-up, a low logic level is applied to the reset pin of third timer 186 to prevent oscillation until a ball passes through the first light panel frame 34.

[0074] When the ball passes through the third light panel frame 38, a logic low is applied to the enable pin of buffer 168, causing the supply voltage V_(cc) at the input to pass to the output, applying a forward bias to transistor switch 166 and turning the switch on. This action triggers first timer 170 and second timer 176, and causes the output states of flip-flop 180 to switch, thereby applying a low logic level to the reset pin of third timer 186, causing third timer 186 to stop oscillating. Consequently, when a ball interrupts the first light panel frame 34, third timer 186 starts oscillating at a frequency of 14650 Hz, the first one hundred and twenty pulses are not counted, and the oscillator 186 stops when the ball interrupts the third light panel frame 38.

[0075]FIG. 17 shows a partial schematic of the speed counter circuit 190. The speed counter circuit 190 counts the pulses generated by the oscillating third timer 186 and determines the speed of a pitch between 50 m.p.h. and 100 m.p.h. A speed over 99 m.p.h. results in a MAX SPEED EXCEEDED lamp 80 being turned on. The speed counter circuit 190 is designed in accordance with the following principles.

[0076] The first light panel frame 34 and the third light panel frame 38 are separated by 14.65 inches. A ball thrown at 100 m.p.h. will take 0.00832 seconds to traverse this distance: $\begin{matrix} {\frac{100\quad {miles}\text{/}{hour}}{3600\quad \sec \text{/}{hour}} = {0.02778\quad {miles}\text{/}\sec}} & (1) \\ {{\frac{0.02778\quad {miles}}{1\quad \sec} \times \frac{5280\quad {feet}}{1\quad {mile}} \times \frac{12\quad {inches}}{1\quad {foot}}} = {1760\quad {inches}\text{/}\sec}} & (2) \\ {\frac{14.65\quad {inches}}{1760\quad {inches}\text{/}\sec} = {0.00832\quad \sec}} & (3) \end{matrix}$

[0077] Since the oscillator 186 puts out 14650 pulses per second, the oscillator will put out about one hundred twenty-one pulses in this period of time (decimal fractions are truncated):

0.00832 sec×14650 pulses/sec=121 pulses  (4)

[0078] The time required to generate 120 pulses is slightly less than 8.225 milliseconds (120 pulses×1/14650 pulses/sec=8.191 milliseconds). By similar calculations, the oscillator puts out 123 pulses for a ball traveling at 99 m.p.h., 124 pulses for a ball at 98 m.p.h., etc. This is summarized in Table 3 as follows: TABLE 3 Speed (m.p.h.) Pulses 100 121 99 123 98 124 97 125 96 127 95 128 94 129 93 131 92 132 91 134 90 135 89 137 88 138 87 140 86 141 85 143 84 145 83 146 82 148 81 150 80 152 79 154 78 156 77 158 76 160 75 162 74 164 73 167 72 169 71 171 70 174 69 176 68 179 67 182 66 184 65 187 64 190 63 193 62 196 61 199 60 203 59 206 58 210 57 213 56 217 55 221 54 225 53 230 52 234 51 239

[0079] It will be seen that the present machine is only designed to measure speeds under 100 m.p.h., therefore the oscillator will always generate at least one hundred twenty pulses, and it is only necessary to count the pulses in excess of one hundred twenty. Hence, timer 176 generates an 8.225 delay pulse which prevents tri-state buffer 182 from passing the first one hundred twenty pulses to the speed counter circuit 190. The speed counter circuit 190 begins receiving pulses with the one-hundred twenty-first pulse, and assumes that if one or two pulses are counted, i.e., less than one hundred twenty-three, the speed is 99 m.p.h; if three pulses are counted, the speed is 98 m.p.h., etc., in accordance with Table 3.

[0080] The speed counter circuit 190 includes a single shift register U18 for determining the first digit (or tens) of the speed and a cascade of shift registers for determining the second digit (or units) of the speed to be displayed. Only three of the units shift registers U14, U19, U20 are shown in FIG. 17, the remaining units shift registers being configured similar to shift registers U19 and U20. The front end of the speed counter circuit is formed by speed switch 76 and a D-type dual flip-flop U13, which are configured so that when the user presses speed switch 76, the master reset lines (pin 9) on all shift registers U14, U18, U19, U20, and subsequent shift registers are triggered to reset all registers. In addition, pins 5 and 6 of flip-flop U13 put a high logic level at the input to shift registers U14 and U18, and also provide a voltage level which is output at 192 and 194 to the display drivers which are dedicated to displaying a “0” in the units and tens of the speed display 88, respectively. Pulses from the oscillator 186 are input through the IN SPD 1 line to the clock pin (pin 8) of the first units shift register U14. The clock pulse shifts the high logic level from the input to the output pin (pin 3) of the first units shift register U14, and puts the high logic level at the input to the second register of U14. The output at pin 3 of U14 also applies a trigger pulse through NAND gate U16 to tri-state buffer G1, thereby providing a clock pulse to pin 8 of shift register U18, shifting the high logic level to output pin 3 of the first register of shift register U18, which is output to a display driver dedicated to displaying a “9” in the tens column of the speed display 88. The output at pin 3 of U14 also provides a voltage output to a display driver dedicated to displaying a “9” on speed display 88. Finally, the output at pin 3 of U14 applies a reset pulse at pin 1 of flip-flop U13, which flip-flops pins 5 and 6 of U13 to remove the high logic level at the input of the first registers and the voltage which displayed “0”'s in the speed display 88.

[0081] Subsequent clock pulses provided by oscillator 186 are shifted through the remaining seven registers of U14 at pins 4, 5, 6, 10, 11, 12, and 13, driving the units column of speed display to show a “9”, “8”, “7”, “6”, “5”, and “4”, respectively, although the register shifts so rapidly that the user does not perceive any changes on the speed display. The tens display remains fixed, keeping a “9” displayed in the tens column, since no additional clock pulse has been applied to pin 8 of U18. When the eighth pulse is felt at the units shift register U14, the output from the last register (pin 13) is cascaded or chained to the input of the first register of shift register U19. When a ninth clock pulse is received from oscillator 136 via the clock bus 196, the output pin (pin 3) of the second units shift register U19 goes high, providing a voltage to a dedicated display driver for displaying a “3” in the units column of speed display 88. Additional clock pulses continue to shift down the output pins of U19's registers in similar fashion.

[0082] When the fifteenth clock pulse from oscillator 186 is received, the display changes from displaying a speed of “90” to displaying a speed of “89”. This is accomplished by tying the output from pin 12 of shift register U19 both to a display driver dedicated to displaying a “9” in the units column of speed display 88, and to a tie point TP connected to the clock pin (pin 8) of U18. When the clock pulse is received by U18, the high logic level output is shifted from the first register output (pin 3) to the second register output (pin 4), which supplies the high level voltage to a display driver dedicated to displaying an “8” in the tens column of the speed display.

[0083] When the seventeenth clock pulse from oscillator 186 is received, the high level output at the output pin (pin 13) of U19 is shifted to the output pin (pin 3) of the first register of third units shift register U20. Subsequent clock pulses continue to shift through the registers of U20, and cascade to subsequent units shift registers (not shown) configured in similar fashion to shift registers U19 and U20. In order to display as speed as low as 50 m.p.h., there are fifteen units shift registers cascaded together (one hundred nineteen pulses with eight registers per shift register).

[0084] The pulses are counted until the ball interrupts a beam on the third frame 38. As described above, this generates a pulse which resets oscillator 136 so that no more pulses are generated. In addition, referring to FIG. 16, flip-flop 180 is reset, causing a high logic level to be output at the OUT SPD 2 line 184, which is received at the IN SPD 2 line in FIG. 17. NAND gate U10 inverts the signal, applying a trigger pulse to trigger pin 6 of dual 556 timer U11. U11 is a cascaded dual timer operating in monostable mode, with the first timer outputting a ten second delay signal which is input to the second timer to trigger a ten microsecond pulse at pin 9 which is coupled by NAND gate U12 and capacitor C17 to the master reset bus (pin 9 of the shift registers U14, U18, U19, U20, etc.), and also to the reset pin of flip-flop U13. This action has the effect of displaying the speed on the speed display 88 for a period of ten seconds, and then resetting the shift registers and resetting the speed display 88 to show “00”.

[0085] In FIG. 17, preferred integrated circuit components include the following: U10, U12, U15, U16, U17 are all two input NAND gates, and may represent single sections of a 74f00 quad 2-input NAND gate chip; U11, is a 556 timer; U13 is a 74f74 D-type flip-flop; U14, U18, U19, and U20 are 74f164 serial in-parallel out shift registers; and G1 is one section of a 74f125 quad tri-state buffer. Preferred values for the remaining components are as shown in the drawing.

[0086] The display panel shows a single lamp display 80 for showing that the baseball has been thrown at a speed greater than the maximum speed that the machine 10 can calculate. FIG. 18 shows the circuitry for driving the single lamp 80. At start-up, the voltage applied to the MAX-1 IN terminal is a logic low and the voltage applied to the MAX-2 IN terminal is at a logic high. This keeps 555 timer U32 disabled. U32 is configured to operate in monostable mode and the values of R30 and C30 are selected to output a ten second logic high pulse when the device is triggered. Referring back to FIG. 16, when a ball interrupts a beam in first light panel frame 34, second timer 176 outputs an 8.225 millisecond logic high pulse to terminal OUT MAX-1 178, which is received at the MAX-1 IN terminal in FIG. 18 and applies a set voltage at pin 4 of U32, so that it is possible to trigger U32 in the 8.225 interval that the logic high voltage is applied to pin 4. If the ball is travelling at 100 m.p.h. or more, a beam in third light panel frame 38 will be interrupted and send a ten microsecond high to low pulse from first timer 170 and inverter 172 out through the OUT MAX-2 terminal 174. This high to low pulse is received in FIG. 18 at the MAX-2 IN terminal and applies a trigger pulse to pin 2 of U32. U32 outputs a ten second logic high pulse, which applies a forward bias to the base of transistor switch Q10, causing Q10 to conduct and apply enough current at the collector to illuminate miniature lamp 80. If the ball does not interrupt a beam in third light panel frame 38 until more than 8.225 milliseconds after the MAX-1 pulse is first felt at pin 4 of U32, i.e., the pitch is slower than 100 m.p.h., then the trigger pulse applied at pin 2 is ineffective, since pin 4 has returned to a low logic level.

[0087] In FIG. 18, a regulated five volt power supply is used to power the 7400 series integrated circuits, but a twelve volt regulated voltage is applied to the collector of Q10 to supply sufficient power to drive the lamp 80. U30, U31 and U33 are AND gates, and may be different sections of a 74f08 quad 2-input AND gate IC. Q10 is preferably a TIP 29 NPN current driver rated for 1 amp at 40 volts. Lamp 80 is a 2.4 volt at 360 milliamp miniature lamp with a threaded base and is mounted in a socket on display panel 18.

[0088] The remaining displays on the display panel 18, e.g., INNING'S 84, OUT'S 86, SPEED 88, etc., utilize a plurality of miniature bulbs arranged in figure eight patterns to display information. As shown in FIG. 19, each figure eight has eighteen bulbs 200 which are arranged in seven segments designated by the dashed lines in the figure. There are two parallel vertical lines, the left line having an upper segment A of three bulbs and a lower segment B of three bulbs, and the right line having an upper segment C of three bulbs and a lower segment D of three bulbs. Further, there are three horizontal segments of two bulbs each, including an upper segment E, a middle segment F, and a lower segment G.

[0089] Each figure eight display has its own dedicated driver circuitry. The driver circuitry for each display is substantially identical. The driver circuitry will therefore be discussed with reference to the driver circuitry for the STRIKES display 94, as shown diagrammatically in FIG. 20. As discussed above with reference to FIG. 14, initially flip-flop 122 outputs a high logic level output which is used by a display driver wired to output a “0” on the strikes display 94. This high logic level or counter pulse 202 is input to a segment selector circuit 204. The segment selector circuit 204 for the output line #0 essentially comprises a NAND gate configured as an inverter, with the output pin tied to the gate pins of seven tri-state buffers or drivers (74f125 quad tri-state buffers may be used) with the output pin of each driver being tied to the power driver circuit 206 for the strike display 94 (one each for segments A, B, C, D, E, and G, and a seventh segment which is complementary to segment F). The power driver circuit 206 for each segment comprises a transistor switch, the bulbs 200 in each segment being in series with the collector of the transistor switch, the output from the buffers providing forward bias to the base of the transistor switches either directly through an AND gate, or indirectly through a NAND gate and a second transistor switch.

[0090] As discussed above with respect to FIG. 14, when the first strike is counted, the output of first register 124 a is a high logic level output which is applied to a display driver wired to output a “1” on the strikes display 94. This high logic level output or counter pulse 208 is applied to a second segment selector circuit 210 having the same general configuration as the first segment selector circuit 204, but having buffer output pins wired to drive the segments necessary to display a “1” (segments C and D). Similarly, the counter pulses from the strike #2 212 and strike #3 216 output lines are input to dedicated segment selector circuits 214 and 216 which provide the necessary bias voltages to the transistor switches in the power driver circuit 206 for lighting the necessary segments A-G on the figure eight strikes display 94.

[0091] The driver circuitry for the other displays have an identical configuration, except that the number of segment selector circuits varies, depending upon how many digits need to be displayed. For example, the WALKS display 90 only requires five selector circuits for displaying the digits from “0” to “4”, while the units column of the SPEED display 88 has ten segment selector circuits for displaying the digits “0” through “9”.

[0092] It will be understood by those skilled in the art that improvements may be made to the pitcher's workout machine within the scope of the present invention. For example, BCD integrated circuits may be used for counting balls, strikes, walks, etc., instead of shift registers. Digital display light emitting diodes and driver integrated circuits may be used in place of miniature lamps for the display. The speed circuit oscillator 186 may be wired to oscillate at a lower frequency, e.g., 4465 Hz with appropriate changes in the following counter circuitry in order to provide for higher time constants, and the input line for the speed lines 160 may be applied directly to pin 3 of dual flip-flop 180, since it's only purpose is to stop oscillation of the third timer 186.

[0093] It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims. 

I claim:
 1. A pitcher's workout machine, comprising: (a) a target frame defining a target zone, the frame having: (i) a first rectangular light panel frame having a first linear array of infrared transmitter-receiver pairs aligned to transmit a light panel of infrared light beams horizontally; (ii) a second rectangular light panel frame having a second linear array of infrared transmitter-receiver pairs aligned to transmit a light panel of infrared light beams vertically, the first and second light panel frames being joined back to back in registry; and (iii) a third rectangular light panel frame having a third linear array of infrared transmitter-receiver pairs aligned to transmit a light panel of infrared light beams horizontally, the third light panel frame being spaced apart from said first and second light panel frames by a predetermined distance; (b) means for determining whether a pitched ball is a ball or strike from the interruption of infrared light beams in the first and second light panels; (c) means for determining the pitched ball's speed from the interruption of infrared light beams in the first and third light panels; and (d) means for displaying whether a pitched ball is a ball or a strike and the speed of the pitched ball; wherein said first, second and third light panel frames each further comprise a linear array of lenses disposed between the transmitter-receiver pairs for focusing the infrared light beams.
 2. The pitcher's workout machine according to claim 1, wherein said second light panel frame has a dead zone with an absence of infrared light beams corresponding to a width of a strike zone centrally disposed in said second linear array.
 3. The pitcher's workout machine according to claim 1, wherein each of said lenses is a convex lens.
 4. The pitcher's workout machine according to claim 1, wherein said first second and third light panel frames each have: (a) a transmitter post, the linear array of transmitters being mounted in said transmitter post; (b) a receiver post parallel to said transmitter post, the linear array of receivers being mounted in said receiver post; and (c) a lens post disposed between said transmitter post and said receiver post, the linear array of lenses being mounted in said lens post.
 5. The pitcher's workout machine according to claim 1, wherein said first linear array of infrared light beams is divided into three zones, including: (a) an upper zone of transmitter-receiver pairs wired to register a ball when a pitched ball interrupts a light beam in the upper zone; (b) a lower zone of transmitter-receiver pairs wired to register a ball when a pitched ball interrupts a light beam in the lower zone; and (c) a middle zone wired to register a strike when a pitched ball interrupts a light beam in the middle zone, provided that the ball does not also interrupt a light beam in the upper zone, lower zone, or second light panel.
 6. The pitcher's workout machine according to claim 1, further comprising: (a) means for determining a walk when four balls have been registered and an out when three strikes have been registered; (b) means for counting an inning when three outs have been registered; and (c) means for displaying walks, outs and innings.
 7. A pitcher's workout machine, comprising: (a) a target having a first panel of infrared light beams and a second panel of infrared light beams spaced apart from said first panel by a predetermined distance; (b) a speed circuit for determining the speed of a ball pitched through said target, including: (i) circuitry connected to said first panel for generating a voltage trigger pulse when a pitched ball interrupts a beam in said first panel; (ii) a timer integrated circuit wired to oscillate and generate a stream of output pulses at a predetermined frequency, the timer having a trigger pin and a reset pin, the timer being triggered to oscillate by said trigger pulse; (iii) circuitry connected to said second panel for generating a stop pulse when a pitched ball interrupts a beam in said second panel, the stop pulse being applied to the reset pin of said timer in order to stop said stream of output pulses; and (iv) a counter circuit, the counter circuit having at least one cascade of shift register integrated circuits, the stream of output pulses being input to the cascade of shift registers, each register in said cascade of shift registers having an output pin connected to a display driver circuit for displaying a digit of the ball's speed as determined by the number of output pulses and the predetermined distance between said first and second panels; and (c) a display having at least one optoelectric display device for displaying digits of the speed of the pitched ball and a display driver circuit connected to the at least one optoelectric device, the output pin of each said register being connected to the display driver circuit.
 8. The pitcher's workout machine according to claim 7, wherein said at least one display device consists of two display devices.
 9. The pitcher's workout machine according to claim 7, wherein said display driver circuit comprises a plurality of drivers, each driver being dedicated to driving the display of a single digit between zero and nine.
 10. The pitcher's workout machine according to claim 7, wherein said speed circuit further comprises: (a) a delay timer connected to said first panel, the delay timer being configured to generate a delay pulse having a duration equal to a period defined by the number of pulses in the stream of output pulses generated by said timer integrated circuit in excess of a maximum speed countable by said speed circuit; and (b) a tri-state buffer having an input pin connected to the stream of output pulses generated by said timer integrated circuit, an output pin connected to said counter circuit, and a reset pin connected to said delay timer; wherein the delay pulse from said delay timer prevents said tri-state buffer from passing the stream of output pulses to said counter circuit so long as the maximum speed is equaled or exceeded.
 11. The pitcher's workout machine according to claim 7, further comprising a maximum speed exceeded optical display device connected to said speed circuit for displaying an optical indication that a pitched ball's speed exceeds a maximum speed capable of being measured by the pitcher's workout machine.
 12. The pitcher's workout machine according to claim 7, wherein said at least one cascade of shift register integrated circuits consists of a first cascade of shift registers for counting speed in increments of ten miles per hour and a second cascade of shift registers for counting speed in increments of one mile per hour, the first cascade being connected to the second so that when the second cascade transitions from a zero to a nine, the first cascade is decremented by ten miles per hour.
 13. The pitcher's workout machine according to claim 7, further comprising: (a) means for determining balls and strikes when a pitched ball transitions said target; (b) means for counting balls, strikes, outs, walks, and innings; (c) means for displaying balls, strikes, outs, walks, and innings.
 14. A pitcher's workout machine, comprising: (a) a frame defining a target zone, the frame having a top; (b) a rack assembly mounted on the top of said frame; (c) a control panel assembly mounted to said rack assembly; (d) a plurality of electronic circuits mounted on said rack assembly, the plurality of electronic circuits including: (i) means for determining a ball from a strike from a location in the target zone where a pitched ball enters the target zone; (ii) means for determining the speed of a pitched ball as it traverses the target zone; (iii) means for counting balls, strikes, outs, walks, and innings; and (e) a display assembly mounted on said rack assembly, the display assembly including: (i) a strikes display device for indicating when a pitched ball is a strike, the display device maintaining a counted total of strikes pitched up to three strikes; (ii) a balls display device for indicating when a pitched ball is a ball, the display device maintaining a count total of balls pitched up to four balls; (iii) an outs display device for indicating a total of outs counted up to three outs; (iv) an innings display device for indicating a total of innings counted up to seven innings; (v) a walks display device for indicating a total of walks counted up to eight walks; and (vi) a speed display device for displaying the speed of a pitched ball.
 15. The pitcher's workout machine according to claim 14, wherein said frame further comprises: (a) a first rectangular light panel frame having a first linear array of infrared transmitter-receiver pairs aligned to transmit a light panel of infrared light beams horizontally; (b) a second rectangular light panel frame having a second linear array of infrared transmitter-receiver pairs aligned to transmit a light panel of infrared light beams vertically, the first and second light panel frames being joined back to back in registry; and (c) a third rectangular light panel frame having a third linear array of infrared transmitter-receiver pairs aligned to transmit a light panel of infrared light beams horizontally, the third light panel frame being spaced apart from said first and second light panel frames by a predetermined distance; wherein said first, second and third light panel frames each further comprise a linear array of lenses disposed between the transmitter-receiver pairs for focusing the infrared light beams.
 16. The pitcher's workout machine according to claim 14, wherein said means for determining the speed of a pitched ball comprises a speed circuit, the speed circuit comprising: (a) circuitry connected to said frame for generating a voltage trigger pulse when a pitched ball enters said frame; (b) a timer integrated circuit wired to oscillate and generate a stream of output pulses at a predetermined frequency, the timer having a trigger pin and a reset pin, the timer being triggered to oscillate by said trigger pulse; (c) circuitry connected to said frame panel for generating a stop pulse when a pitched ball exits said frame, the stop pulse being applied to the reset pin of said timer in order to stop said stream of output pulses; and (d) a counter circuit, the counter circuit having at least one cascade of shift register integrated circuits, the stream of output pulses being input to the cascade of shift registers, each register in said cascade of shift registers having an output pin connected to a display driver circuit for displaying a digit of the ball's speed as determined by the number of output pulses.
 17. The pitcher's workout machine according to claim 14, further comprising a maximum speed exceeded optical display device connected to said speed circuit for displaying an optical indication that a pitched ball's speed exceeds a maximum speed capable of being measured by the pitcher's workout machine.
 18. The pitcher's workout machine according to claim 14, wherein said plurality of electronic circuits are mounted on circuit boards disposed on said rack assembly, the plurality of circuit boards including: (a) a power supply board; (b) a transmitter board; (c) a receiver board; (d) a main logic board; and (e) a display driver board. 